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Espressif Systems /ESP32-C6 /ECC /MULT_CONF

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Interpret as MULT_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (RESET)RESET 0 (KEY_LENGTH)KEY_LENGTH 0 (SECURITY_MODE)SECURITY_MODE 0 (CLK_EN)CLK_EN 0WORK_MODE 0 (VERIFICATION_RESULT)VERIFICATION_RESULT 0 (MEM_CLOCK_GATE_FORCE_ON)MEM_CLOCK_GATE_FORCE_ON

Description

ECC configure register

Fields

START

Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done.
RESET

Write 1 to reset ECC Accelerator.
KEY_LENGTH

The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
SECURITY_MODE

Reserved
CLK_EN

Write 1 to force on register clock gate.
WORK_MODE

The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
VERIFICATION_RESULT

The verification result bit of ECC Accelerator, only valid when calculation is done.
MEM_CLOCK_GATE_FORCE_ON

ECC memory clock gate force on register

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data